A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, an array of memory cells for NAND flash memory is arranged such that a control gate of each memory cell in a row of the array is connected to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line.
A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
One way of increasing the density of memory devices is to form stacked memory arrays, e.g., often referred to as three-dimensional (3D) memory arrays. For example, one type of three-dimensional memory array may include pillars of stacked memory elements, such as substantially vertical NAND strings.
Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the disclosure scope or to specific invention embodiments is thereby intended.